Title :
A response compactor for extended compatibility scan tree construction
Author :
You, Zhiqiang ; Huang, Jiedi ; Inoue, Michiko ; Kuang, Jishun ; Fujiwara, Hideo
Author_Institution :
Software Sch., Hunan Univ., Changsha, China
Abstract :
Though test application time and test power is reduced drastically in the extended compatibility scan tree, the number of output is too large. This paper proposes a response compactor to reduce its output number as well as the test response data volume. This compactor is composed by an XOR network. Exploring the characteristic of extended compatibilities and the structure information of the circuit under test, it can effectively solve error diffusion problem, and achieves low hardware overhead. Experimental results show the applicability of the response compactor. As for the ISCAS´89 benchmark circuits, the compactor can have the highest compression ratio to 77 while keeping the same fault coverage.
Keywords :
comparators (circuits); design for testability; logic gates; logic testing; ISCAS´89 benchmark circuits; XOR network; circuit under test; design for testability; extended compatibility scan tree construction; fault coverage; response compactor; solve error diffusion problem; Benchmark testing; Circuit faults; Circuit testing; Compaction; Costs; Design for testability; Hardware; Integrated circuit technology; Integrated circuit testing; Very large scale integration; XOR network; design for testability; full scan testing; scan tree; test response compaction;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351359
