Soft error filtered and hardened latch

This paper presents a low-power soft error-hardened latch suitable for reliable circuits. The proposed circuit uses redundant feedback loop to protect latch circuit against soft error on the internal nodes and skewed CMOS to filter out transients resulting from particle hit on combinational logic. The proposed circuit has low power consumption, enhanced setup time and lower timing overhead. The HSPICE post-layout simulations in 90 nm CMOS technology reveals that circuit is able to recover from single particle strike on internal nodes and tolerates input SETs up to 130 ps of duration.