Title :
An 0.35μm/ CMOS 2.4Gb/s LVDS for high-speed DAC
Author :
Huang, Xingfa ; Li, Liang ; Xu, Kaikai ; Li, Ruzhang ; Shu, Cheng
Author_Institution :
Nat. Labs. of Analog Integrated Circuits, Chongqing, China
Abstract :
In the light of application to high-speed DAC, the design and achievement of a novel high-performance CMOS LVDS receiving circuits are described in this paper. By introduction of intrinsic offset, a fixed hysteresis voltage is obtained. The whole circuit doesn´t need any local feedback, and the high-speed performance of the original circuit doesn´t change with introduction of hysteresis voltage. Therefore the circuit has twofold advantages: a stable hysteresis voltage and a high-speed operation. The circuit was developed in chartered 0.35 μm CMOS process technology. The tested results showed that the circuit worked stably at an operational voltage of 3.3 V at a transmission speed of 2.4 Gb/s. The chip size of the circuit was 0.021 mm2, and the power consumption of the circuit was 8 mW.
Keywords :
CMOS integrated circuits; digital-analogue conversion; D/A converter; bit rate 2.4 Gbit/s; chartered CMOS process technology; digital-analogue converter; fixed hysteresis voltage; high-performance CMOS LVDS receiving circuits; high-speed DAC; low-voltage differential signaling technology; power 8 mW; power consumption; size 0.35 μm; voltage 3.3 V; CMOS process; CMOS technology; Circuit testing; Energy consumption; Feedback circuits; Hysteresis; Voltage; LVDS D/A converter; high-speed I/O;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351442
