Gap-closing test structures for temperature budget determination

We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer thicknesses of SOI and metal, lateral silicidation can be enforced. Using this principle, test structures with dedicated designs exhibit a much larger (thus easier to quantify) resistance change over time. Using novel test structures this approach of thermal budget determination spans a larger temperature range as compared to bulk-silicon substrates. Theory, test structure design and measurement results are presented using Pd layers on silicon-on-insulator substrates.