Title :
High-performance pMOSFETs with high-k gate dielectric and dislocation-free epitaxial Si/Ge super-lattice channel
Author :
Liu, Li-Jung ; Chang-Liao, Kuei-Shu ; Fu, Chung-Hao ; Hsieh, Hsiao-Chi ; Lu, Chun-Chang ; Wang, Tien-Ko ; Gu, P.Y. ; Tsai, M.J.
Author_Institution :
Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ~ 1 nm. The source/drain activation temperature at 650 °C is especially suitable for high-k gate dielectric process.
Keywords :
Ge-Si alloys; MOSFET; dislocations; elemental semiconductors; epitaxial growth; hole mobility; semiconductor growth; superlattices; EOT value; Id-Vg curve; SL virtual substrate; Si-Ge; dislocation-free epitaxial superlattice channel; electrical characteristics; high-k gate dielectric processing; high-performance pMOSFET; on-off ratio; pMOSFET device; peak hole mobility; source-drain activation temperature; temperature 650 degC; Epitaxial growth; Logic gates; MOSFET circuits; MOSFETs; Silicon; Silicon germanium;
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2012 IEEE
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0996-7
Electronic_ISBN :
2161-4636
DOI :
10.1109/SNW.2012.6243324
