A new full adder design for tree structured arithmetic circuits

Author

Jiang, Jian-Fei ; Mao, Zhi-gang ; He, Wei-feng ; Wang, Qin

Author_Institution

Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China

Volume

4

fYear

2010

fDate

16-18 April 2010

Abstract

A new low power and high speed full adder is designed which targets at tree structured applications. By employing complementary signal at input, buffer inverter at output, a new transmission gate based full adder is proposed. This new adder uses 20 transistors to achieve high driving ability and low power consumption. Simulation in Semiconductor Manufacturing International Corporation 0.18-μm CMOS process indicates that the new adder outperforms the four existing adders in terms of power delay product. The design has a full voltage swing, making it suitable for technology scaling. The adder can be used for high-performance circuits such as high speed and low power multipliers.

Keywords

CMOS logic circuits; adders; digital arithmetic; invertors; logic design; logic gates; low-power electronics; CMOS process; Semiconductor Manufacturing International Corporation; buffer inverter; full voltage swing; high speed full adder design; high-performance circuits; low power consumption; low power full adder design; low power multipliers; power delay product; size 0.18 mum; transistors; transmission gate based full adder; tree structured arithmetic circuits; Adders; Arithmetic; CMOS process; Circuit simulation; Delay; Energy consumption; Inverters; Manufacturing processes; Semiconductor device manufacture; Virtual manufacturing; full adder; high speed; low power; multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Engineering and Technology (ICCET), 2010 2nd International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6347-3

Type

conf

DOI

10.1109/ICCET.2010.5485618

Filename

5485618