Single-phase adiabatic flip-flops and sequential circuits with power-gating scheme

This paper presents the implementations of adiabatic flip-flops and sequential circuits using single-phase power-clock with power-gating scheme. All circuits are realized by using the improved single-phase CAL (clocked adiabatic logic) technology. A power-gating scheme for the improved CAL circuits is used to reduce energy dissipation in sleep mode. All circuits are implemented using Chartered 0.35 ¿m CMOS technology, and full-custom layouts are drawn. Based on the HSPICE simulations with post-layout extracted parasitic, the single-phase adiabatic sequential circuits with the power-gating scheme attain large energy savings over a wide range of frequencies, as compared with conventional CAL circuits and improved CAL circuits.