Low-power realization of FIR filters using current-mode analog design techniques

This work demonstrates the feasibility of low-power analog FIR filters using current-mode techniques. Preliminary results from the proposed filter indicate a power consumption that is much lower than alternate digital implementations at 20MSPS making it attractive for portable applications. The FIR filter comprises of a current-mode sample-and-hold configured as a delay element followed by an analog multiplier. Results from an 8-tap linear phase filter and a 16-tap non-linear phase filter are shown to match well with the ideal filter responses.