Title :
A parallel intra prediction architecture for H.264 video decoding
Author :
Wang, Xi ; Cui, Xiaoxin ; Yu, Dunshan
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
In this paper, an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 video coding standard is adopted. The hardware design is based on a novel organization of the intra prediction equations. Compared with conventional architecture, intra predict efficiency is enhanced. The Verilog RTL is verified to work at 103 MHz in a Xilinx II FPGA.
Keywords :
hardware description languages; video coding; H.264 video decoding; Verilog RTL; Xilinx II FPGA; parallel intra prediction architecture; real-time implementation; Decoding; Equations; Hardware design languages; MPEG standards; Microelectronics; Pipelines; Prediction algorithms; Video coding; Video compression; Video sharing; H.264; decoding; hardware; intra prediction;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351558
