A power and area efficient architecture of convolver based on ram

Author

Chen, Chen ; Chen, Yun ; Chen, Yuan ; Pan, An ; Zeng, Xiao-Yang

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

835

Lastpage

838

Abstract

This paper proposes a novel architecture of the convolver which can also be used as a correlator (depend on the order in which the input sequence are put in). It is power and area efficient compared with the typical architectures based on registers. Two groups of convolver are implemented to show the improvement. One group deals with two 12 bit data sequences of length 64, while another deals with two 12 bit data sequences of length 256, with each group containing a ram based one and a conventional one. The synthesis results by DC using SMIC 0.13 um library and the results of Prime Power shows that in the second group, the area and power of the ram based one can be reduced to 91% and only 77% of the conventional one, respectively.

Keywords

computer architecture; correlators; random-access storage; RAM; SMIC; area efficient architecture; convolver; correlator; power efficient architecture; Application specific integrated circuits; Convolution; Convolvers; Correlators; Delay; Digital signal processing; Finite impulse response filter; Hydrogen; Libraries; Registers; Convolver; area; correlator; power; ram; register;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351564

Filename

5351564