Title :
A design of level interface for CMP based Cache system
Author :
Chen, Chen ; He, Hu ; Liu, Yuan
Author_Institution :
Tsinghua Nat. Lab. of Inf. & Technol., Tsinghua Univ., Beijing, China
Abstract :
This paper proposes a level interface for two-level cache sub-system based on a 4-core CMP system. This interface module successfully connects L1-Cache and L2-Cache. Several optimizations are utilized in the design, which contribute to the realization of high-efficient communication between the two levels, lowering L1-Cache miss penalty, and the improvement of processing efficiency of access requests.
Keywords :
cache storage; microprocessor chips; multiprocessing systems; CMP system; cache system; chip multiprocessor; level interface; Degradation; Design methodology; Design optimization; Helium; Logic design; Microelectronics; Multicore processing; Random access memory; Read-write memory; Timing; Cache; Miss Penalty; Multi-port; Pipeline;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351565
