Effect of Bit Precision on Hardware Complexity for DDFS Architecture

This paper proposes an analysis of bit resolution versus the hardware complexity of a novel CORDIC (coordinate rotational digital computer) architecture, which acts as DDFS (direct digital frequency synthesizer). The analysis will help us reaching a point which is optimum as far as bit resolution Vs mean square error is concerned. Further more it will conclude that an increase in bit resolution does not really help in reducing the mean square error there fore making hardware more complex is not advise, compactness of hardware is directly proportional to area and power consumption as well.