A self correcting low jitter non-sequential phase detector

This paper describes a novel technique of phase detection using only non-sequential elements that can be used in clock and data recovery (CDR) circuits. CDR circuits typically employ a phase locked loop (PLL) or a delay locked loop (DLL) when a reference clock is available at exactly the same frequency of the transmitted data. CDR circuits using a PLL use either a linear phase detector or a non-linear phase detector depending on design parameters like jitter tolerance and data transmission speeds. Most linear and non-linear phase detectors in CDR circuits are implemented by using sequential elements and latches that easily fall into the metastable region at high speeds thereby increasing the jitter in locked conditions. In this paper a novel linear phase detector is presented which uses only non sequential elements and delays to achieve lock.