Design and FPGA implementation of 3DES against Power Analysis Attacks for IC bankcard

The power analysis attacks have become a major threat to the cryptographic chips, especially in financial fields. Many countermeasures against these attacks have been proposed, and most of these countermeasures are focused on the microcontroller-based implementations. In this paper, a novel VLSI design of 3DES circuit is achieved for IC bankcard, and "random insertion of dummy cycles" is used against power analysis attacks. Compared with the pure 3DES circuit, the extra cost for performance and extra area are significantly lowered by design optimization. The design has been verified to be feasible by FPGA, and it can keep the secret key secure under the differential power analysis attacks when the amount of power traces is less than 22,000.