Title :
Uniform routing architecture for FPGA with embedded IP cores
Author :
Wang, Liyun ; Wang, Yuan ; Chen, Liguang ; Wang, Jian ; Chen, Xing ; Wu, Fang ; Lai, Jinmei ; Tong, Jiarong
Abstract :
A uniform routing architecture is presented, which offers CLB, IOB and IP Cores an identical routing resource. At the same time, some method is adopted to optimize routing performance. With all unidirectional segmented lines and long lines with inserted tap buffers, this architecture is up to 9.8% faster compared with long lines without inserted buffers and on average 14.9% over bidirectional lines. Simulation results demonstrate our idea.
Keywords :
field programmable gate arrays; logic design; network routing; CLB; FPGA; IOB; IP cores; unidirectional segmented lines; uniform routing architecture; Delay; Fabrics; Field programmable gate arrays; Multiplexing; Multiprocessor interconnection networks; Parallel processing; Reconfigurable architectures; Reconfigurable logic; Routing; Signal processing algorithms; FPGA; long line with inserted buffers; unidirectional segmented lines; uniform routing architecture;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351594
