Title :
VLSI implementation of a new block cipher
Author :
Bonnenberg, H. ; Curiger, A. ; Felber, N. ; Kaeslin, H. ; Lai, X.
Author_Institution :
Swiss Federal Inst. of Technol., Zurich, Switzerland
Abstract :
The high speed architecture for a VLSI implementation of a new smart-key block cipher is presented. The chip performs data encryption and decryption in a single hardware unit. It runs with a maximum clock frequency of 33 MHz permitting a data conversion rate of more than 55 Mb/s. This high data rate, compared to currently available DES (data encryption standard) implementations, has been achieved by implementing a pipelined architecture and by using a sophisticated data scheduling scheme guaranteeing a continuously fully loaded pipeline
Keywords :
VLSI; cryptography; standards; 33 MHz; 55 Mbit/s; VLSI implementation; block cipher; data encryption; data encryption standard; data scheduling scheme; decryption; high speed architecture; pipelined architecture; smart-key; Cryptography; Hardware; Laboratories; Microelectronics; Pipeline processing; Signal design; Signal processing; Standards publication; Throughput; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139960
