Design of a high reliable L1 data cache with redundant cache

Modern high-performance processors utilize cache memory systems to tolerate the increasing latency of main memory. Along with IC technology improvement, complicated cache memory systems in processors are very vulnerable to soft errors under severe environment. To deal with multiple soft errors with little impact on hardware overhead and performance, this paper proposes a new cache memory system, in which redundant cache blocks are integrated into a set-associative L1 data cache. Each redundant cache block is used to store the replica of each ¿dirty¿data in correspondence with L1 data cache blocks. In order to realize the detection of multiple soft errors with little hardware overhead, a bit interleaving group parity code is adopted to detect multiple soft errors in L1 data cache blocks. Moreover, in order to increase the mapping rate between L1 data cache blocks and the redundant cache blocks, an early write-back based protocol is introduced, in which all dirty cache blocks are written back to L2 cache at the intervals of a determined cycle number. The proposed cache system can provide more powerful soft error protection than conventional error correction codes. Experiment results show that the cache system proposed in this paper can provide replicas for almost 100% of dirty cache blocks in L1 data cache on average.