DocumentCode
2655528
Title
Switching activity calculation of VLSI adders
Author
Baran, Dursun ; Aktan, Mustafa ; Karimiyan, Hossein ; Oklobdzija, Vojin G.
Author_Institution
Univ. of Texas at Dallas, Richardson, TX, USA
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
46
Lastpage
49
Abstract
Using exact switching activity rates at all internal nodes when calculating energy of digital circuits is believed to result in improved accuracy over to the use of average switching activity.We compare the two approaches in the case of the Kogge-Stone adder implemented with Weinberger and Ling addition recurrences. The difference between the two is less than 4%.Further we examined the accuracy of the energy/delay estimation technique when using exact and average switching activities in 65 nm, 45 nm, 32 nm and 22 nm technology nodes. Even then the worse case error in estimating energy is under 15% at 22 nm technology node for 64-bit Kogge-Stone adder. The error in delay estimation is less than 6% for all the nodes. Our finding is that using average switching activity does not yield large errors while simplifying the estimation process greatly.
Keywords
VLSI; adders; delay estimation; switching circuits; Kogge-Stone adder; Ling addition; VLSI adders; Weinberger addition; delay estimation; digital circuits; internal nodes; switching activity calculation; Adders; Delay estimation; Digital circuits; Driver circuits; Energy consumption; Energy efficiency; Logic circuits; Switching circuits; Very large scale integration; Yield estimation; Digital Circuits; Energy Consumption; Energy-Delay Estimation; Switching Activity;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351611
Filename
5351611
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