Title :
Low power design of vlsi circuits and systems
Author :
Zhao, Peiyi ; Wang, Zhongfeng
Author_Institution :
Math & Comput. Sci. Dept., Chapman Univ., Orange, CA, USA
Abstract :
Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 2008. Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focus discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems.
Keywords :
VLSI; circuit optimisation; clocks; integrated circuit design; low-power electronics; ITRS 2008; VLSI circuit design; circuit level method; clocking system; low-power optimization technique; Circuits and systems; Clocks; Design optimization; Energy consumption; Flip-flops; Frequency; Latches; Power dissipation; System performance; Very large scale integration; VLSI; clocking system; flipflop; low power;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351616
