A jitter insensitive continuous-time ΣΔ modulator using transmission lines

This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows us to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1% of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators.