DocumentCode
2655803
Title
Electromigration-dependent parametric yield estimation
Author
Barsky, Roman ; Wagner, Israel A.
Author_Institution
Dept. of Comput. Sci., Technion-Israel Inst. of Technol., Haifa, Israel
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
121
Lastpage
124
Abstract
We define and investigate the problem of electromigration faults caused by spot defects during the VLSI manufacturing process. Analysis is given for a simple layout, and simulations are presented and discussed for a more complicated case. It is shown that in some cases, electromigration-dependent parametric faults can make a significant contribution to the total yield estimation.
Keywords
VLSI; electromigration; integrated circuit yield; VLSI manufacturing process; electromigration faults; electromigration-dependent parametric faults; parametric yield estimation; spot defects; total yield estimation; Analytical models; Circuit faults; Computational modeling; Computer science; Electromigration; Frequency estimation; Manufacturing processes; Very large scale integration; Wire; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
Print_ISBN
0-7803-8715-5
Type
conf
DOI
10.1109/ICECS.2004.1399629
Filename
1399629
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