Title :
Area optimization for higher order hierarchical floorplans
Author :
The, Khe-Sing ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. An algorithm for general hierarchical floorplans is presented. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a shape curve are determined by simultaneously reducing the length of all longest paths of the vertical adjacency graph, using a minimum cut technique. The algorithm is applicable to hierarchical floorplans of high order and to modules with an infinite set of possible dimensions
Keywords :
circuit layout CAD; optimisation; area optimization; graph representations; higher order hierarchical floorplans; minimum cut technique; nonslicing configurations; shape curves; vertical adjacency graph; Algorithm design and analysis; Approximation algorithms; Circuit topology; Flexible printed circuits; Heuristic algorithms; Iterative algorithms; Piecewise linear approximation; Piecewise linear techniques; Shape;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139963
