DocumentCode
2655859
Title
3D power grid modeling
Author
Zlydina, Larissa ; Yagil, Yoad
Author_Institution
M.T.M. Sci. Industries Center, Intel Corp., Haifa, Israel
fYear
2004
fDate
13-15 Dec. 2004
Firstpage
129
Lastpage
132
Abstract
The paper describes on-chip 3D power grid (PG) modeling for high performance CPU designs. We show that for high frequencies (above 1 GHz) it is necessary to use the full RLM PG model with extracted partial self and mutual conductors\´ inductances, rather than resistive R or RL models. We also present a practical model reduction technique named "real space reduction" (RSR), which enables simplifying the model and reduces memory and simulation time without significant accuracy losses.
Keywords
VLSI; inductance; microprocessor chips; power supply circuits; reduced order systems; 3D power grid modeling; RLM PG model; extracted partial self inductance; high performance CPU; model reduction technique; mutual conductor inductance; real space reduction; Conductors; Frequency; Geometry; Inductance; Packaging; Power grids; Power system modeling; Variable structure systems; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
Print_ISBN
0-7803-8715-5
Type
conf
DOI
10.1109/ICECS.2004.1399631
Filename
1399631
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