Title :
Implementation of LDPC decoder for 802.16e
Author :
Peng, Xiao ; Goto, Satoshi
Author_Institution :
Grad. Sch. of Inf., Production & Syst. of Waseda Univ., Waseda, Japan
Abstract :
The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interconnection requirements. In this paper, we investigate the approaches to realize Turbo Decoding Message Passing (TDMP) algorithm. We compare the performance and implementation complexity of original approach, Jacobian approach, normalized min-sum approach and offset min-sum approach which are targeted for Quasi-Cyclic (QC) LDPC code defined in IEEE 802.16e standard. The normalized and offset approaches are more suitable for hardware implementation, which are realized on the FPGA.
Keywords :
broadband networks; message passing; parity check codes; radio networks; turbo codes; FPGA; IEEE 802.16e; Jacobian approach; LDPC decoder; low-density parity-check codes; normalized min-sum approach; offset min-sum approach; turbo decoding message passing algorithm; Channel capacity; Code standards; Concatenated codes; Field programmable gate arrays; Hardware; Iterative algorithms; Iterative decoding; Jacobian matrices; Message passing; Parity check codes; LDPC; TDMP; min-sum;
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
DOI :
10.1109/ASICON.2009.5351628
