DocumentCode :
2655981
Title :
Area minimization of MPRM circuits
Author :
Li, Hui ; Wang, Pengjun ; Dai, Ling
Author_Institution :
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
fYear :
2009
fDate :
20-23 Oct. 2009
Firstpage :
521
Lastpage :
524
Abstract :
In the minimization of the Mix Polarity Reed-Muller expression (MPRM) circuits, MPRM with different polarities can be got directly from a given Sum-Of-Product expression (SOP). Based on Kronecker Functional Decision Diagrams (KFDDs), a Polarity Conversion Technique (PCT) is proposed. MPRM under a desired polarity is obtained using PCT algorithm, then an Exhaustive-search Technique based on Gray Code (ETGC) is developed. ETGC algorithm is used for deriving MPRM with all polarities. Some experiments are performed comparing with optimizing the Fixed Polarity Reed-Muller expression (FPRM). Simulation results show that the minimal MPRM is smaller than FPRM, the average area savings is 60.7%.
Keywords :
Gray codes; Reed-Muller codes; logic circuits; network synthesis; search problems; Gray code; Kronecker functional decision diagrams; MPRM circuits; area minimization; exhaustive-search technique; mix polarity Reed-Muller expression circuits; polarity conversion technique; sum-of-product expression; Boolean functions; Circuit simulation; Circuit synthesis; Circuit testing; Circuits and systems; Field programmable gate arrays; Logic testing; Minimization methods; Programmable logic arrays; Reflective binary codes; Circuit; KFDDs; MPRM; Minimization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location :
Changsha, Hunan
Print_ISBN :
978-1-4244-3868-6
Electronic_ISBN :
978-1-4244-3870-9
Type :
conf
DOI :
10.1109/ASICON.2009.5351633
Filename :
5351633
Link To Document :
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