Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design

As CMOS technology is scaled down to below 90 nm, interconnection lines on a complicated chip plays a key role in speed/frequency and performance. The conventional coplanar interconnection structure has good high-frequency performance, but the chip area is large. This will significantly increase chip area of a complicated system-on-chip (SOC) which require many interconnection lines. In this research, the optimal structure of interconnection lines for nano-CMOS technology with multi-layer metals is proposed and analyzed. It is found from simulation results that multi-layer non-coplanar interconnection lines with signal line at the top layer metal and ground line at a lower layer metal without planar space between lines have the optimal performance of transmission loss, frequency response, and chip area. An experimental chip is designed to verify the simulation results. The proposed new interconnection structure can be applied to nano-CMOS SOC design.