Strained Si n-FET featuring compliant SiGe Stress Transfer Layer (STL) and Si0.98C0.02 source/drain stressors for performance enhancement

Author

Wang, Grace Huiqi ; Toh, Eng-Huat ; Weeks, Doran ; Landin, Trevan ; Spear, Jennifer ; Tung, Chih Hang ; Thomas, Shawn G. ; Samudra, Ganesh ; Yeo, Yee-Chia

Author_Institution

Nat. Univ. of Singapore, Singapore

fYear

2007

fDate

12-14 Dec. 2007

Firstpage

1

Lastpage

2

Abstract

We report the first demonstration of an n-channel transistor (n-FET) featuring a compliant Si_0.75Ge_0.25 stress transfer layer (STL) and in situ doped Si_0.98C_0.02 source/drain (S/D) stressors for performance enhancement. Due to the stress coupling between Si_0.98C_0.02 and the compliant SiGe STL, additional strain is imparted to the Si channel. Devices with gate length LG down to 30 nm were fabricated. The enhanced strain effects resulted in 65% drive current improvement in strained n-FETs over control n-FETs for a given DIBL of 0.20 V/V.

Keywords

Ge-Si alloys; elemental semiconductors; field effect transistors; semiconductor materials; silicon; Si; Si_0.98C_0.02; SiGe; device performance enhancement; n-channel transistor; source-drain stressors; strain effects; strained n-FET; stress coupling; stress transfer layer; CMOS technology; Capacitive sensors; Fabrication; Germanium silicon alloys; Lattices; Silicon germanium; Strain control; Stress; Substrates; Tensile strain;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2007 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-1892-3

Electronic_ISBN

978-1-4244-1892-3

Type

conf

DOI

10.1109/ISDRS.2007.4422229

Filename

4422229