DocumentCode
2657010
Title
On-state and switching performance investigation of sub-50nm L-DUMGAC MOSFET design for high-speed logic applications
Author
Chaujar, Rishu ; Kaur, Ravneet ; Saxena, Manoj ; Gupta, Mridula ; Gupta, R.S.
Author_Institution
Univ. of Delhi, Delhi
fYear
2007
fDate
12-14 Dec. 2007
Firstpage
1
Lastpage
2
Abstract
In this paper, an extensive study on the on-state and switching behavior of laterally amalgamated dual material gate concave (L-DUMGAC) MOSFET (Fig.l) is performed and the influence of technology variations, such as gate length, negative junction depth (NJD) and gate bias has been investigated using ATLAS device simulator.
Keywords
MOSFET circuits; high-speed integrated circuits; integrated circuit modelling; logic circuits; ATLAS device simulator; L DUMGAC MOSFET; gate length; high speed logic applications; laterally amalgamated dual material gate concave MOSFET; negative junction depth; on state behavior; switching performance; Logic design; MOSFET circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Device Research Symposium, 2007 International
Conference_Location
College Park, MD
Print_ISBN
978-1-4244-1892-3
Electronic_ISBN
978-1-4244-1892-3
Type
conf
DOI
10.1109/ISDRS.2007.4422275
Filename
4422275
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