Image correlation using a bit level systolic array

Author

Peisl, U.

Author_Institution

Siemens AG, Munich, West Germany

fYear

1988

fDate

7-9 Jun 1988

Firstpage

2689

Abstract

The author describes a bit-serial systolic array architecture based on simple one-bit pipelined processing cells for real-time image correlation. Due to the high sampling rates (up to 40 MHz) and the large data streams, the implementation of image processing algorithms such as two-dimensional correlation requires dedicated chips. The proposed bit-serial architecture includes an optimized scheme for inner-product computation that realizes a speed and area improvement over a previous method. A chip has been designed to compute the two-dimensional correlation function in synchronization with the scanning rate of industrial TV cameras for gray-scale TV images

Keywords

cellular arrays; computerised picture processing; correlation methods; digital signal processing chips; parallel architectures; pipeline processing; 2D correlation; TV cameras; TV images; bit-serial architecture; bit-serial systolic array; computerised picture processing; image correlation; image processing; parallel architecture; pipelined processing; Cameras; Computer architecture; Computer industry; Gray-scale; Image processing; Image sampling; Optimization methods; Streaming media; Systolic arrays; TV;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo

Type

conf

DOI

10.1109/ISCAS.1988.15494

Filename

15494