A robust offset cancellation scheme for analog multipliers [utilises digital integrator]

A new robust offset cancellation scheme for analog multipliers is presented. The offset signal is extracted from the multiplier output using a digital integrator and is fed back to the input for cancellation. This scheme cancels the offset at both the inputs of analog multipliers. The cancellation circuitry is simple and mostly digital, so is suitable for on-chip implementation. The circuit and a Gilbert multiplier are designed in TSMC 0.18 μm CMOS technology to verify the scheme. Schematic simulation shows that the cancellation can greatly attenuate the DC offset and harmonics.