A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

We develop a quantum mechanical model for electron mobility, including Coulomb scattering of carriers and surface roughness in scaled high-K, metal-gate, NMOS transistors, which predicts an increase in Coulomb scattering mobility and a slow decrease of surface roughness mobility with increasing the gate voltage. The total mobility is limited by the bulk mobility because of the need for highly-doped substrates for scaled 45nm node transistors.