Optimal resizing of bus wires in layout migration

The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of processing technology, because wire resistance and cross capacitances become more important with scaling. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the total area of the whole bus structure is regarded as a fixed constraint. Properties of optimal bus layouts are proven, and an iterative algorithm to find the optimal wire widths and spaces is presented. Examples of solutions are shown. Guidelines for design are derived from these results.