Design-for-testability for synchronous sequential circuits using locally available lines

Proposes a non-scan design-for-testability (DFT) method to increase the testability of synchronous sequential circuits. Non-scan DFT allows at-speed testing, as opposed to scan or partial-scan based DFT that normally leads to low-speed testing and longer test application times due to scan operations. The proposed method is based on the identification of several types of restrictions imposed by the combinational logic of the circuit on the values that can be assigned to the next-state variables. These restrictions limit the set of states the circuit can reach, thus limiting the set of input patterns that can be applied to its combinational logic during normal operation. This in turn limits the fault coverage that can be achieved. The proposed DFT procedure is different from other non-scan based DFT procedures in that it relies on lines available locally to drive the inserted DFT logic, avoiding the routing of primary input lines to the flip-flops, and the routing of internal lines to the primary outputs