Corner lot process variation effects on high speed ADCs for satellite receivers

In summary, we have demonstrated fully integrated high-speed ADC performance characteristics with process variations. The ADC corner lot study verified that process variations such from poly resistors and BJT-β and emitter area size can affect the ADC dynamic performance. The optimum ADC performances were achieved by setting the corner process as Lot 6 conditions which are maximum BJT-β and minimum BJT emitter area, while keeping the poly resistors values and without changing the ADC chip design.