Performance improvement of edge-triggered sequential circuits

The paper presents a novel delay insertion method to improve the performance of edge-triggered sequential circuits through clock skew scheduling. Clock skew scheduling (CSS) is performed on synchronous circuits in order to increase the maximum operating frequency. With CSS, the original circuit topology is preserved while the clock distribution network is modified to satisfy an optimal clock skew schedule. The paper proposes a circuit modification technique consisting of delay insertion into logic paths in order to improve the minimum possible clock period. In experiments, improvements of up to 90% are observed over the zero clock skew, flip-flop based circuits for the selected ISCAS´89 suite of benchmark circuits.