DocumentCode :
2658864
Title :
A high-speed CMOS op-amp design technique using negative Miller capacitance
Author :
Shem-Tov, Boaz ; Kozak, Mücahit ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Ort Braude Coll., Karmiel, Israel
fYear :
2004
fDate :
13-15 Dec. 2004
Firstpage :
623
Lastpage :
626
Abstract :
A method is presented in this paper for the design of high speed CMOS operational amplifiers (op-amp). The op-amp consists of an operational transconductance amplifier (OTA) followed by an output buffer. The OTA is compensated with a capacitor connected between the input and output of the buffer. An op-amp is designed in a 0.18 μm standard digital CMOS technology and exhibits 86 dB DC gain. The unity gain frequency and phase margin are 392 MHz and 73°, respectively, for a parallel combination of 2 pF and 1 kΩ load. As compared to the conventional approach, the proposed compensation method results in a 1.5 times increase in unity gain frequency and a 35° improvement in the phase margin under the same load conditions.
Keywords :
CMOS analogue integrated circuits; UHF amplifiers; buffer circuits; compensation; differential amplifiers; integrated circuit design; operational amplifiers; 0.18 micron; 1 kohm; 2 pF; 392 MHz; 86 dB; OTA; buffer input-output connected capacitor; compensation method; fully-differential operational amplifier; high-speed CMOS op-amp; internally compensated OTA; negative Miller capacitance; operational transconductance amplifier; output buffer; phase margin; Bandwidth; CMOS technology; Capacitance; Capacitors; Circuit noise; Contracts; Frequency; Operational amplifiers; Signal to noise ratio; Transconductance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2004. ICECS 2004. Proceedings of the 2004 11th IEEE International Conference on
Print_ISBN :
0-7803-8715-5
Type :
conf
DOI :
10.1109/ICECS.2004.1399758
Filename :
1399758
Link To Document :
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