An architecture-oriented routing method for FPGAs having rich hierarchical routing resources

We have developed an architecture-oriented routing method for a telecommunications FPGA (Field-Programmable Gate Array) which has rich hierarchical routing resources. Our routing method consists of four routing procedures, each of which are related to a specific part of the routing resource architecture of the FPGA. It can accomplish routing results almost five times faster than a reference method that does not consider the routing resource architecture. The key idea in our approach is to reduce the number of possible resource candidates by referring to both the logical net structure and the FPGA resource architecture. We apply different routing algorithms according to the amount and architecture of candidate routing resources. Experiments show that our architecture-oriented method is more effective than conventional single-algorithm-based methods