Impacts of a buffer layer and hi-wafers on the performance of strained-channel NMOSFETs with SiN capping layer

In this study, we propose the electrical characteristics of nMOSFETs with local strained channel technique using SiN capping layer on Hi- or Cz-wafers. The nMOSFETs were fabricated on 6-in Hi- and Cz- wafers. Before passivation layer deposition, a 300 nm LPCVD SiN was deposited (denoted as SiN/Cz and SiN/Hi), while some wafers were deliberately skipped of the SiN deposition step to serve as the controls (denoted as Cz-control and Hi). For some SiN-capped nMOSFETs, a thin LPCVD-TEOS buffer layer (about 7 nm, denoted as SiN/Buffer/Cz and SiN/Buffer/Hi) was capped prior to the SiN deposition.