Title :
On the optimal sub-routing structures of 2-D FPGA greedy routing architectures
Author :
Pan, Jiaofeng ; Wu, Yu-Liang ; Wong, C.K.
Author_Institution :
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Abstract :
For the FPGA Greedy Routing Architectures (GRAs), the optimal mapping problem of the entire chip can be decomposed into a sequence of three kinds of optimal m-side predetermined 4-way FPGA mapping problems, where m could be 1, 2, or 3. In this paper, we formulate the graph models of such sub-routing problems and investigate their minimum structures. The results give the lower bounds of routing resources in achieving all such kinds of GRAs and the theoretic models developed could be useful to studies on other FPGA routing problems as well
Keywords :
circuit layout CAD; field programmable gate arrays; graph theory; logic CAD; network routing; FPGA Greedy Routing Architectures; FPGA mapping; graph models; lower bounds; optimal mapping; routing resources; sub-routing; Computer architecture; Computer science; Field programmable gate arrays; Flip-flops; Logic arrays; Pins; Routing; Switches; Table lookup; Wire;
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
DOI :
10.1109/ASPDAC.1998.669544
