Mismatch compensation in current mirrors with FGMOS transistor

This paper presents a technique to solve mismatch compensation problems in current mirrors using the floating gate MOS transistor. To reduce mismatches, the tunneling and injection processes are applied in a 1.2 μm CMOS process. It takes into account the long-term voltage storage as charge on the floating gate of a transistor pMOS. Experimental results justifying these processes are also including. The output current of the current mirror present successful results according to theorical analysis and achieving the mismatch compensation.