Large current enhancement in n-MOSFETs with strained Si on insulator

As scaling of the critical transistor dimensions below 65 nm has been slowed down, the implementation of novel materials, especially high mobility channel materials is most attractive to boost the transistor performance. Applying strain to silicon has become a successful route. The electron mobility can be enhanced by biaxial strain introduced into Si by epitaxial growth of Si on a strain relaxed SiGe layer or by so called process induced methods applied directly on transistor level. The combination of strained Si and SOI is particularly promising due to the combination of the enhanced mobilities and the inherent advantages of SOI. First long channel n-MOSFETs with gate lengths of 5 to 50 mum and a 6.6 nm thick SiO₂ gate dielectric were fabricated. For comparison, devices on unstrained SOI were made. The transfer characteristics of a fully depleted sSOI-MOSFET with a gate length of 5 mum and a gate width of 20 mum indicating an inverse sub-threshold slope of 75mV/dec.