Temperature dependent empirical modeling of proximity diffused Si esaki diodes and memory circuits

Author

Pawlik, D.J. ; Muhkerjee, S. ; Krom, R. ; Pandharpure, S. ; Kurinec, S.K. ; Anisha, R. ; Berger, P.R. ; Rommel, S.L.

Author_Institution

Dept. of Microelectron. Eng., Rochester

fYear

2007

fDate

12-14 Dec. 2007

Firstpage

1

Lastpage

2

Abstract

In this paper, the modified Sze model developed by the authors fits the measured IV characteristics very well for both forward and reverse biases at temperatures ranging from 23degC up to 200degC. Simulations of a TSRAM timing diagrams at multiple temperatures show the viability of using the developed model for accurate simulation and characterization of tunnel diode augmented CMOS circuits, including temperature effects.

Keywords

CMOS integrated circuits; SRAM chips; elemental semiconductors; semiconductor device models; silicon; tunnel diodes; CMOS circuits; IV characteristics; Si; TSRAM timing diagrams; memory circuits; modified Sze model; proximity diffused Si Esaki diodes; temperature dependent empirical modeling; temperature effects; tunnel diode; Circuits; Educational institutions; Germanium silicon alloys; Resonance; Resonant tunneling devices; Semiconductor device modeling; Semiconductor diodes; Semiconductor process modeling; Silicon germanium; Temperature dependence;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2007 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-1891-6

Electronic_ISBN

978-1-4244-1892-3

Type

conf

DOI

10.1109/ISDRS.2007.4422455

Filename

4422455