Carrier-transport-enhanced CMOS using new channel materials and structures

While the mobility is still an important parameter to describe the current drive under sub-100 nm regime, the reduction in the effective mass is more essential in increasing the on-current under ballistic or near-ballistic transport. When applying those technologies to future technology nodes, we need to take into account the following issues; (1) successive increase in carrier transport properties with a progression in technology nodes, (2) individual optimization of nMOS and pMOS channel structures and (3) compatibility with multi-gate structures. This paper reviews our recent results on these carrier-transport-enhanced CMOS structures on the Si platform for future high performance and low power LSIs.