DocumentCode :
2660587
Title :
VLSI implementation of pipelined linear system solver
Author :
Jou, I-Chang ; Tsay, Shuh-Chuan ; Tseng, Chih-Yuan ; Liu, Ron-Yi
Author_Institution :
Telecommun. Lab., Minist. of Commun., Chung-Li, Taiwan
fYear :
1988
fDate :
7-9 Jun 1988
Firstpage :
2699
Abstract :
A linear rotation-based algorithm without pivoting for solving linear system equations of the form Ax=b is presented. This algorithm modifies the conventional Gaussian elimination method and avoids the problems of numerical singularity and ill conditioning. It is shown that this algorithm can be implemented with a trapezoid-type array with n2/2+(n-2) processors, and a linear array with n processors, where n is the rank of this linear system. The former array performs the triangularization of matrix A using the modified linear rotation algorithm, and the latter array carries out the backward substitution for evaluating the solution of x. The computing time for solving linear system equations will be O(5n) time units. The architecture is simple, uniform, and regular, so it is well suited for implementation in VLSI
Keywords :
VLSI; cellular arrays; computational complexity; mathematics computing; matrix algebra; parallel algorithms; parallel architectures; pipeline processing; VLSI; computing time; linear rotation algorithm; matrix; parallel architecture; pipelined linear system solver; systolic architecture; trapezoid-type array; triangularization; Computer architecture; Digital signal processing chips; Equations; Linear systems; Matrices; Performance evaluation; Real time systems; Signal processing algorithms; Vectors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
Type :
conf
DOI :
10.1109/ISCAS.1988.15496
Filename :
15496
Link To Document :
بازگشت