A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology

Author

Chen, Wei-Zen ; Lu, Tai-You ; Wang, Yan-Ting ; Jian, Jhong-Ting ; Yang, Yi-Hung ; Huang, Guo-Wei ; Liu, Wen-De ; Hsiao, Chih-Hua ; Lin, Shu-Yu ; Liao, Jung Yen

Author_Institution

Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

13-15 June 2012

Firstpage

12

Lastpage

13

Abstract

A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3^rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm². This chip drains 24mW from a 1.2V power supply.

Keywords

CMOS integrated circuits; indicators; millimetre wave receivers; nanoelectronics; phase locked loops; 3<;sup>;rd<;/sup>; harmonic mixer; CMOS technology; chip size; fast locking; frequency 156.4 GHz to 160 GHz; frequency acquisition; frequency down conversion; frequency locking time; frequency sweeping; frequency tripler; power 24 mW; receiver-based phase-locked loop; signal strength indicator; size 65 nm; voltage 1.2 V; CMOS integrated circuits; Harmonic analysis; Mixers; Phase locked loops; Power harmonic filters; Voltage-controlled oscillators; Mixer; PLL; RSSI; THz;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243765

Filename

6243765