Dual independent cell generation

A two-stage linear-time optimization algorithm is presented for dual independent layout styles. The first stage is based on a new tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization algorithm is applicable to many VLSI layout styles. The algorithm is applied to the M ³ layout style, and examples of generated layouts are shown. Starting from a switching expression, the algorithm always produces an optimal solution, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence such that the layout contains a minimum number of diffusion gaps (second stage)