• DocumentCode
    2661113
  • Title

    Hierarchical floorplanning and detailed global routing with routing-based partitioning

  • Author

    Ohmura, Michiroh ; Wakabayashi, Shin´ichi ; Toyohara, Yoshihiro ; Miyao, Jun´ichi ; Yoshida, Noriyoshi

  • Author_Institution
    Fac. of Eng., Hiroshima Univ., Japan
  • fYear
    1990
  • fDate
    1-3 May 1990
  • Firstpage
    1640
  • Abstract
    A hierarchical floorplanning method is presented in which it is possible to determine simultaneously a floorplan and detailed global routes which directly correspond to switchboxes and channels. In this method, since the precise estimation of congestion of channels and switchboxes is possible, no extremely congested channels and switchboxes are created. Experimental results show that the method can produce an optimal floorplan in terms of congestion
  • Keywords
    VLSI; circuit layout CAD; integrated circuit technology; network topology; CAD; VLSI layout; channel congestion estimation; channel routeing; global routing; hierarchical floorplanning; routing-based partitioning; switchboxes; Logic circuits; Partitioning algorithms; Routing; Shape; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1990., IEEE International Symposium on
  • Conference_Location
    New Orleans, LA
  • Type

    conf

  • DOI
    10.1109/ISCAS.1990.112452
  • Filename
    112452
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2661113