A 0.6V 2.9µW mixed-signal front-end for ECG monitoring

Author

Yip, Marcus ; Bohorquez, Jose L. ; Chandrakasan, Anantha P.

Author_Institution

Massachusetts Inst. of Technol., Cambridge, MA, USA

fYear

2012

fDate

13-15 June 2012

Firstpage

66

Lastpage

67

Abstract

This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-V_T digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.

Keywords

CMOS analogue integrated circuits; biomedical electronics; delta-sigma modulation; digital signal processing chips; electrocardiography; interference suppression; patient monitoring; ΔΣ-modulation; CMOS process; ECG monitoring; SAR ADC; aggressive voltage scaling; analog circuits; dual-DAC architecture; frequency 50 Hz; frequency 60 Hz; fully-integrated front-end; interference cancellation; low-voltage DSP; mixed-signal ECG front-end; mixed-signal feedback; near-voltage digital processing; power 2.9 muW; power-efficiency; power-hungry ADC buffer; size 0.18 mum; ultralow-voltage operation; voltage 0.6 V; Band pass filters; Clocks; Digital signal processing; Electrocardiography; IEC standards; Monitoring; Noise;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243792

Filename

6243792