Accurate speed improvement techniques for RC line and tree interconnections in CMOS VLSI

A physical delay model for small-geometry CMOS inverters with RC tree interconnection networks is presented. Through extensive comparisons with SPICE simulation results, it is shown that the maximum relative error in delay-time calculations using the model is within 15% for 1.5-μm CMOS inverters with RC tree interconnection networks. Moreover, the model has a wide applicable range of circuit and device parameters. An experimental sizing program is constructed for speed improvement of interconnection lines and trees. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed improvement techniques and determine the suitable sizes and/or number of drivers/repeaters for a minimum delay. It is found that the required tapering factor in cascaded drivers is not e (the base of the natural logarithm) but a value in the range 4-8. Moreover, adding a small number of drivers/repeaters with large size is more efficient in reducing the interconnection delay. It is also shown that the technique of optimal-size repeaters with cascaded input drivers can lead to the lowest delay