A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

Author

Tan, Y. ; Duster, J. ; Fu, C.-T. ; Alpman, E. ; Balankutty, A. ; Lee, C. ; Ravi, A. ; Pellerano, S. ; Chandrashekar, K. ; Kim, H. ; Carlton, B. ; Suzuki, S. ; Shafi, M. ; Palaskas, Y. ; Lakdawala, H.

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2012

fDate

13-15 June 2012

Firstpage

76

Lastpage

77

Abstract

A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF power amplifiers; analogue-digital conversion; digital-analogue conversion; phase locked loops; radio transceivers; ADC; DAC; DPLL; EVM; IIP3; OSR; SoC CMOS technology; T-R Switch; WLAN Transceiver; bit rate 240 Mbit/s; bit rate 320 Mbit/s; bit rate 54 Mbit/s; efficiency 12.5 percent; efficiency 19.7 percent; fractional LOG; frequency 2.4 GHz; fully-integrated highly-linear PA; noise figure 4.8 dB; relaxed filtering; size 32 nm; voltage 1.8 V; CMOS integrated circuits; Mixers; Radio frequency; Switching circuits; System-on-a-chip; Transceivers; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243797

Filename

6243797